/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-18 10:54:28
 *
 */


#ifndef IPA_CLK_CORE_H
#define IPA_CLK_CORE_H

#define CTL_BASE_IPA_CLK_CORE 0x21050000


#define REG_IPA_CLK_CORE_CGM_IPA_CORE_CFG    ( CTL_BASE_IPA_CLK_CORE + 0x0020 )
#define REG_IPA_CLK_CORE_CGM_IPA_MTX_CFG     ( CTL_BASE_IPA_CLK_CORE + 0x0024 )
#define REG_IPA_CLK_CORE_CGM_IPA_APB_CFG     ( CTL_BASE_IPA_CLK_CORE + 0x0028 )
#define REG_IPA_CLK_CORE_CGM_PCIE2_AUX_CFG   ( CTL_BASE_IPA_CLK_CORE + 0x002C )
#define REG_IPA_CLK_CORE_CGM_PCIE3_AUX_CFG   ( CTL_BASE_IPA_CLK_CORE + 0x0030 )
#define REG_IPA_CLK_CORE_CGM_USB_REF_CFG     ( CTL_BASE_IPA_CLK_CORE + 0x0034 )
#define REG_IPA_CLK_CORE_CGM_USB_PIPE_CFG    ( CTL_BASE_IPA_CLK_CORE + 0x0038 )
#define REG_IPA_CLK_CORE_CGM_USB_UTMI_CFG    ( CTL_BASE_IPA_CLK_CORE + 0x003C )
#define REG_IPA_CLK_CORE_CGM_PCIE2_PIPE_CFG  ( CTL_BASE_IPA_CLK_CORE + 0x0040 )
#define REG_IPA_CLK_CORE_CGM_PCIE3_PIPE_CFG  ( CTL_BASE_IPA_CLK_CORE + 0x0044 )
#define REG_IPA_CLK_CORE_CGM_IPA_TIMER_CFG   ( CTL_BASE_IPA_CLK_CORE + 0x0048 )
#define REG_IPA_CLK_CORE_CGM_UART_CFG        ( CTL_BASE_IPA_CLK_CORE + 0x004C )
#define REG_IPA_CLK_CORE_CGM_TIMER_26M_CFG   ( CTL_BASE_IPA_CLK_CORE + 0x0050 )
#define REG_IPA_CLK_CORE_CGM_32K_OUT_CFG     ( CTL_BASE_IPA_CLK_CORE + 0x0054 )

/* REG_IPA_CLK_CORE_CGM_IPA_CORE_CFG */

#define BIT_IPA_CLK_CORE_CGM_IPA_CORE_CFG_CGM_IPA_CORE_SEL(x)       (((x) & 0x3))

/* REG_IPA_CLK_CORE_CGM_IPA_MTX_CFG */

#define BIT_IPA_CLK_CORE_CGM_IPA_MTX_CFG_CGM_IPA_MTX_DIV(x)         (((x) & 0x3) << 8)

/* REG_IPA_CLK_CORE_CGM_IPA_APB_CFG */

#define BIT_IPA_CLK_CORE_CGM_IPA_APB_CFG_CGM_IPA_APB_DIV(x)         (((x) & 0x3) << 8)

/* REG_IPA_CLK_CORE_CGM_PCIE2_AUX_CFG */

#define BIT_IPA_CLK_CORE_CGM_PCIE2_AUX_CFG_CGM_PCIE2_AUX_SEL        BIT(0)

/* REG_IPA_CLK_CORE_CGM_PCIE3_AUX_CFG */

#define BIT_IPA_CLK_CORE_CGM_PCIE3_AUX_CFG_CGM_PCIE3_AUX_SEL        BIT(0)

/* REG_IPA_CLK_CORE_CGM_USB_REF_CFG */

#define BIT_IPA_CLK_CORE_CGM_USB_REF_CFG_CGM_USB_REF_SEL            BIT(0)

/* REG_IPA_CLK_CORE_CGM_USB_PIPE_CFG */

#define BIT_IPA_CLK_CORE_CGM_USB_PIPE_CFG_CGM_USB_PIPE_PAD_SEL      BIT(16)

/* REG_IPA_CLK_CORE_CGM_USB_UTMI_CFG */

#define BIT_IPA_CLK_CORE_CGM_USB_UTMI_CFG_CGM_USB_UTMI_PAD_SEL      BIT(16)

/* REG_IPA_CLK_CORE_CGM_PCIE2_PIPE_CFG */

#define BIT_IPA_CLK_CORE_CGM_PCIE2_PIPE_CFG_CGM_PCIE2_PIPE_PAD_SEL  BIT(16)

/* REG_IPA_CLK_CORE_CGM_PCIE3_PIPE_CFG */

#define BIT_IPA_CLK_CORE_CGM_PCIE3_PIPE_CFG_CGM_PCIE3_PIPE_PAD_SEL  BIT(16)

/* REG_IPA_CLK_CORE_CGM_IPA_TIMER_CFG */

#define BIT_IPA_CLK_CORE_CGM_IPA_TIMER_CFG_CGM_IPA_TIMER_SEL        BIT(0)

/* REG_IPA_CLK_CORE_CGM_UART_CFG */

#define BIT_IPA_CLK_CORE_CGM_UART_CFG_CGM_UART_DIV(x)               (((x) & 0x7) << 8)
#define BIT_IPA_CLK_CORE_CGM_UART_CFG_CGM_UART_SEL                  BIT(0)

/* REG_IPA_CLK_CORE_CGM_TIMER_26M_CFG */

#define BIT_IPA_CLK_CORE_CGM_TIMER_26M_CFG_CGM_TIMER_26M_SEL        BIT(0)

/* REG_IPA_CLK_CORE_CGM_32K_OUT_CFG */

#define BIT_IPA_CLK_CORE_CGM_32K_OUT_CFG_CGM_32K_OUT_SEL            BIT(0)


#endif /* IPA_CLK_CORE_H */


